This invention relates to terminators which are applicable to metal oxide semiconductors on insulator (MOS-soi) with triple wells integrated circuit technology and which are particularly useful for terminator networks.
For signal interfaces between devices terminators have been used, as described for instance in U.S. Pat. No. 4,748,426: entitled xe2x80x9cActive termination circuit for computer interface usexe2x80x9d, granted May 31, 1998 to Alexander Stewart for Rodime PLC, in an active termination circuit for a computer interface for reducing line reflection of logic signals. Such terminators have used a first and second resistor combination to permanently connect to a signal line that couples a plurality of peripheral devices to one another. The other ends of the first and second resistors are connected through a switching device to a positive voltage supply line and to logic ground, respectively. When termination of multiple devices was required, a plurality of resistor combinations were provided but on/off control of the switch in this example was achieved by one control that is located remote from the termination circuit systems. Integrated circuit interconnection structures have also used precision terminating resistors, as illustrated by U.S. Pat No. 4,228,369, granted in October, 1980 to Anantha et al. for IBM.
As will be illustrated for chip interconnection, when resistor terminators are used in thin film semiconductor integrated circuits such as those used in metal oxide semiconductors (e.g.CMOS) today, they create hot spots which cannot be adequately cooled, so such resistor terminator circuits which create hot spots cannot be used in metal oxide semiconductor applications to provide terminators for chip to chip connections on chips using IBM""s new sub-micron MOS (CMOS) technologies where because of the high currents used in these networks it is difficult or impossible to meet all the cooling and reliability requirements required for commercial performance. It has become necessary to invent a solution to interfacing devices which can be used in such environments on chips, and used for terminators in networks of chips and devices where there is a need to transmit digital data therebetween without overshoot and undershoot in signal transmission between the chips and devices or systems. These connections need to operate at a faster speed, accommodating data rate speeds ranging into hundreds of Mhz and Ghz.
The creation of a terminator which particularly may be fabricated for high speed metal oxide semiconductor on insulator (MOS-soi) applications with triple wells in integrated circuits is needed.
The described invention provides the needed terminator and receiver network, and particularly a circuit which provides a well balanced threshold voltage between the logic levels, so that maximum noise tolerance between logic levels can be achieved for the receiver in a digital system.
As a result of the circuit illustrating the preferred embodiment of the invention, a terminator network which is well adapted for MOS manufacture is provided that can match the characteristic impedance of the line to which the terminator network is connected. This invention relates to terminator network which is useful for fast transmission of digital data, eliminating or reducing overshoot and undershoot in signal transmission between chips and between systems, in serial links and data buses, for minimizing ringing and similar noise problems, for providing electrostatic discharge (ESD) protection, particularly in high speed metal oxide semiconductor (MOS) integrated circuit applications, and mixed vender technology interface communications. The circuit meets the demand for fast data transmission has push the data rate into hundreds of Mhz and Ghz. It is advantages for reducing the signal swing so that the signal reach its desired voltage levels for digital ones or zeros defining voltage levels faster with lower power and with less noise generation at the high digital transmission speeds. It operates in the multiple hundred MHz and Ghz ranges.
The circuit provides a terminator and receiver network which is fast and suitable for small signal swings and may also be manufactured for coupling cups with mixed technologies for high speed communication. The network is particularly adapted for MOS and SOI-MOS circuits, providing a network that can match the characteristic impedance of the transmission line. The new terminator network has low current flow and low power consumption. The terminator network provides electrostatic discharge protection for the chipset at the input of an attached circuit. Also, the circuit allows switching into high impedance so that a the driver of a coupled circuit can take control of the communication line and drive out for the bi-directional data buses that are necessary in computer systems today.
In providing the circuit described, the user able to turn off all currents to support standard CMOS leakage tests so that chips with defects can be found quickly and easily in manufacture and assembly of chipsets.
The receiver in the present circuit can properly receive small signals, and it also has balanced noise tolerance between logic levels. ESD protection is provided at the input of the circuit.
These and other improvements are set forth in the following detailed description. For a better understanding of the invention with advantages and features, refer to the description and to the drawings.